Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Networkon- Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support doublebinary codes, by exploiting bit-level and pseudo-floatingpoint representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 d

A DTMC Model for Performance Evaluation of Irregular Interconnection Networks with Asymmetric Spatial Traffic Distributions

Several mathematical models have been proposed to evaluate the performance of interconnection networks used for high-speed connections for supercomputers, switches and routers for local and wide area networks, as well as networks on a chip. Often these models are based on state space reduction by exploiting symmetries of the network and requiring uniform traffic patterns. If an interconnection network is built for a specific application with non-uniform spatial traffic distribution, models that are more general are needed. This paper proposes a mathematical model for performance evaluation of application-specific interconnection networks based on inhomogeneous discrete time Markov chains (DTMC). It supports store and forward routing, irregular network topologies, and asymmetric spatial traffic distributions. The model is described in a generalized way so that it can support arbitrary switching element sizes within the network and its input buffers